Method of manufacturing interconnect

ABSTRACT

A method of manufacturing an interconnect. A wafer having an edge region and an interior region is provided. An insulating layer is formed on the wafer. An opening penetrating through the insulating layer in the interior region is formed and a portion of the insulating layer is removed to expose the surface of the wafer in the edge region, simultaneously. A conductive layer is formed on the insulating layer and the wafer exposed by the insulating layer and fills the opening. The conductive layer is patterned to form a wire in the opening.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the priority benefit of Taiwanapplication serial no. 88103922, filed Mar. 15, 1999, the fulldisclosure of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a method of manufacturing asemiconductor device. More particularly, the present invention relatesto a method of manufacturing an interconnect.

[0004] 2. Description of the Related Art

[0005] Due to the increasingly high integration of ICs, chips simplycannot provide sufficient area for manufacturing interconnections.Therefore, in accord with the increased interconnect manufacturingrequirements of miniaturized MOS transistors, it is increasinglynecessary for IC manufacturing to adopt a design with more than twometal layers. In particular, a number of multi-function products, suchas microprocessors, may even require 4 or 5 metal layers to complete theinternal connections thereof. Generally, an inter-metal dielectric (IMD)layer is used to isolate electrically two adjacent metal layers fromeach other.

[0006] In order to perform an interconnection more easily and totransfer the pattern more precisely, it is important to have a waferwith an even topography. Since the probability of inaccuracy of thealignment system can be reduced by using a wafer with a relatively eventopography, the fine pattern can be transferred more accurately.

[0007]FIGS. 1A through 1B are schematic, cross-sectional views of theconventional pattern transfer process.

[0008] As shown in FIG. 1A, a substrate having a conductive layer 120,wires 120 a and 120 b and a insulating layer 122 formed thereon isprovided. A dotted line I-I divides a wafer (not shown) into two parts.One side of the dotted line I-I, denoted as region 116, is the interiorregion of the wafer, wherein the interior region has effective dies. Theother side of the dotted line I-I, denoted as region 118, is the edgeregion of the wafer. The dies in the region 118 are incompletely formed,so that the region 118 is a region having ineffective dies. Since thedistribution density of the conductive layer 120 is higher than that ofthe wires 120 a and 120 b, the ability of portions of the insulatinglayer 122 in the region 118 to resist the planarization step is higherthan that in the region 118. Hence, portions of the insulating layer 122in the region 116 are thicker than the portions of the insulating layer122 in the region 116 after chemical-mechanical polishing (CMP). Becausethe region 118 is higher than the region 116, a sloped surface 124 ofthe insulating layer 122 above the wire 120 a is shown in the region 116adjacent to the region 118. In highly integrated ICs, theinterconnection is more than one layer, so that the step height betweenthe regions 118 and 116 is increasingly larger.

[0009] As shown in FIG. 1B, a photoresist 128 is formed on theinsulating layer 122. Photolithography is performed to form openings 130a and 130 b in the photoresist 128, respectively aligned with the wires120 a and 120 b. The opening 130 b may be formed to expose theunderlying dielectric layer 122 since the photoresist 128 is within therange of depth of focus (DOF). The DOF range is from the optimum focusBF to the maximum AF at both sides of the optimum focus BF. As theportion of the photoresist 128 over the wire 120 a is higher and beyondthe DOF, so that an error occurs for the photolithography process. As aconsequence, the opening 130 a fails to expose by the dielectric layer122. This is called scumming. Additionally, the defocusing happens sincea conductive layer subsequently formed on the region 118 is relativelyhigh and beyond the DOF. Therefore, the conductive layer caves.

[0010] Generally, the step height of the photoresist caused by theprofile of only one conductive layer is about 1000-3000 angstroms, whichis an allowable error range. In other words, difference between thephotoresist 128 in the region 118 and in the region 116 is about1000-3000 angstroms. However, the step height increases as the number ofthe conductive layers increases. Therefore, the step height is more than6000-7000 angstroms beyond the tolerable range. Hence, the scummingeasily happened and it is difficult to accurately transfer a finepattern from the photomask to the wafer.

SUMMARY OF THE INVENTION

[0011] The invention provides a method of manufacturing an interconnect.By using the invention, the problem of scumming can be overcome and thethroughput can be greatly enhanced.

[0012] To achieve these and other advantages and in accordance with thepurpose of the invention, as embodied and broadly described herein, theinvention provides a method of manufacturing an interconnect. A waferhaving an edge region and an interior region is provided. An insulatinglayer is formed on the wafer. An opening penetrating through theinsulating layer in the interior region is formed and a portion of theinsulating layer is removed to expose the surface of the wafer in theedge region, simultaneously. A conductive layer is formed on theinsulating layer and the wafer exposed by the insulating layer and fillsthe opening. The conductive layer is patterned to form a wire in theopening. Since the insulating layer in the edge region of the wafer islower than that in the interior region of the wafer and the slopedsurface of the insulating layer is in the edge region, a fine patterncan be more accurately transferred from the photomask into theinsulating layer. The problem of scumming can be also overcome.Moreover, the throughput can be greatly enhanced by using the invention.

[0013] It is to be understood that both the foregoing generaldescription and the following detailed description are exemplary, andare intended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention. In the drawings,

[0015]FIGS. 1A through 1B are schematic, cross-sectional views of theconventional pattern transfer process; and

[0016]FIGS. 2A through 2L are schematic, cross-sectional views of theprocess for manufacturing an interconnect in a preferred embodimentaccording to the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] Reference will now be made in detail to the present preferredembodiments of the invention, examples of which are illustrated in theaccompanying drawings. Wherever possible, the same reference numbers areused in the drawings and the description to refer to the same or likeparts.

[0018]FIGS. 2A through 2L are schematic, cross-sectional views of theprocess for manufacturing an interconnect in a preferred embodimentaccording to the invention.

[0019] As shown in FIG. 2A, an insulating layer 202 and a photoresist204 are formed on a substrate 200 in sequence. The insulating layer 202can be an inter-layer dielectric layer (IDL) or inter-metal dielectriclayer (IMD) and the photoresist layer 204 can be a positive photoresist,for example. A dotted line II-II divides a wafer (not shown) into twoparts. One side of the dotted line II-II denoted as region 216 is theinterior region of the wafer, wherein the interior region has effectivedies. The other side of the dotted line II-II denoted as region 218 isthe edge region of the wafer. The dies in the region 218 are incomplete,so that the region 218 is a region having ineffective dies.

[0020] As shown in FIG. 2B, a first exposure step is performed to exposea portion of the photoresist 204 in the region 216 by a light 217 a in astepper with a photomask 215. The pattern is transferred from thephotomask 215 into the photoresist 204 through the first exposure step.

[0021] As shown in FIG. 2C, a second exposure step is performed toexpose the photoresist 204 in the region 218 by a light 217 b in astepper. In this example, the region 218 can be exposed without using amask or by using a blank mask. The second exposure step and the firstexposure step can be performed in the different steppers, for example.

[0022] As shown in FIG. 2D, a development step is performed on thephotoresist 204 and the pattern on the photomask 215 is transferred tothe photoresist 204 in the region 216. Therefore, portions of thephotoresist 204 in the regions 216 and 218 are removed to exposeportions of the insulating layer 202 in the regions 216 and 218 and thepatterned photoresist 204 is denoted as photoresist 204 a.

[0023] As shown in FIG. 2E, portions of the insulating layer 202 in theregion 216 is removed to form openings 206 a and 206 b by using thephotoresist 204 a as an etching mask until a portion of the substrate200 is exposed by the openings 206 a and 206 b. Simultaneously, theportion of the insulating layer 202 in the region 218 is removed toexpose a portion of the substrate 200 in the region 218. The insulatinglayer 202 having opening 206 a and 206 b and uncovering the portion ofthe insulating layer in the region 218 is denoted as insulating layer202 a. The openings 206 a and 206 b can be via holes or node contactholes, for example. The photoresist 204 is removed to expose theinsulating layer 202 a.

[0024] As shown in FIG. 2F, a conductive layer 220 is formed on thesubstrate 200 exposed by the insulating layer 202 a and on theinsulating layer 202 a and fills the openings 206 a and 206 b. Thematerial of the conductive layer 220 can be a metal or polysilicon, forexample. The thickness of the conductive layer 220 is about 5000angstroms.

[0025] As shown in FIG. 2G, the conductive layer 220 is patterned toform conductive layer 220 c, wires 220 a and 220 b, respectively on thesubstrate 200 exposed by the insulating layer 202 a and in the openings206 a and 206 b. An insulating layer 224 with low permittivity is formedover the substrate 200. The insulating layer 224 is formed by chemicalvapor deposition, for example. Preferably, the method of forming theinsulating layer 224 can be high density plasma chemical vapordeposition (HDPCVD). Since the insulating layer 224 has lowpermittivity, it can provide good isolation between wires 220 a and 220b. Because the wires 220 a and 220 b are slightly higher than thesurface of the insulating layer 202 a, the surface of the insulatinglayer 224 is not smooth.

[0026] As shown in FIG. 2H, an insulating layer 226 is formed on theinsulating layer 224. The insulating layer 226 can be formed by chemicalvapor deposition, for example. Preferably, the method of forming theinsulating layer 226 can be plasma enhancement chemical vapor deposition(PECVD). The insulating layers 224 and 226 together form an insulatinglayer 222. Since the portion of the insulating layer 224 above the wires220 a and 220 b are relatively thick, the topography of the insulatinglayer 224 is rough. Therefore, the topography of the insulating layer226 formed on the insulating layer 224 is uneven.

[0027] As shown in FIG. 2I, a planarization step is performed toplanarize the insulating layer 226. The planarization step can be CMP.Since the region 218 is lower than the region 216, the region 218 isslightly lower than the region 216 after the planarization step. Hence,a sloped surface 226 a of the insulating layer 222 is shown in theregions 218 adjacent to the region 216. In the other words, the portionof the insulating layer 226 above the wires 220 a and 220 b is veryeven.

[0028] As shown in FIG. 2J, a patterned photoresist 228 having openings230 a and 230 b is formed on the insulating layer 222. The openings 230a and 230 b are respectively aligned with the wires 220 a and 220 b.Because of the very even insulating layer 226 above the wires 220 a and220 b, a portion of the photoresist 228 above the wires 220 a and 220 bis within the DOF range and the scumming will not happen. Hence, theopenings 230 a and 230 b are vertical to the insulating layer 222 andexpose a portion of the insulating layer 222 above the wires 220 a and220 b.

[0029] As shown in FIG. 2K, a portion of the insulating layer 222 isremoved to form openings 232 a and 232 b by using the patternedphotoresist 228 as an etching mask. The openings 232 a and 232 bpenetrate through the insulating layer 222 and respectively expose thewires 220 a and 220 b. The openings 232 a and 232 b can be via holes ornode contact holes, for example. The patterned photoresist 228 isremoved.

[0030] As shown in FIG. 2L, a conductive layer 234 is formed on theinsulating layer 222 and fills the openings 232 a and 232 b.

[0031] In the invention, when other interconnection layers are formed onthe conductive layer 234, the process of forming the interconnectionlayers is the same as the process shown from FIGS. 2A through 2L. In theother words, a portion of the insulating layers above the conductivelayer 234 in the region 218 is removed, which is the same as theformation of the insulating layer 204 a. In this example, the method ofremoving a portion of the insulating layer in the region 218 can be usedfor alternating insulating layers.

[0032] In the invention, since the edge region of the wafer is lowerthan the interior region of the wafer and the sloped surface of theinsulating layer and the photoresist is in the edge region, theinsulating layer in the edge region is in the DOF range. Therefore, afine pattern can be transferred from the photomask into the insulatinglayer more accurately and the problem of scumming is overcome. Moreover,the loss ratio of effective dies in the interior region of the wafer byusing the conventional method is about 15 percent. However, by using theinvention, the throughput can be greatly enhanced by about 20 percent.

[0033] It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the present inventioncover modifications and variations of this invention provided they fallwithin the scope of the following claims and their equivalents.

What is claimed is:
 1. A method of manufacturing an interconnect on awafer, wherein the wafer has an edge region and an interior region, themethod comprising the steps of: forming an insulating layer on the waferhaving an interior region and a edge region; forming an openingpenetrating through the insulating layer in the interior region andremoving a portion of the insulating layer to expose a surface of thewafer in the edge region, simultaneously; forming a conductive layer onthe insulating layer and the wafer exposed by the insulating layer andfilling the opening; and patterning the conductive layer to form a wirein the opening.
 2. The method of claim 1 , wherein the opening includesa via hole.
 3. The method of claim 1 , wherein the opening includes anode contact hole.
 4. The method of claim 1 , wherein the step offorming the opening and removing the portion of the insulating layercomprises the steps of: forming a positive photoresist on the insulatinglayer; performing a first exposure step to from a first exposure regionin the positive photoresist above the subsequently formed opening;performing a second exposure step to form a second exposure region inthe positive photoresist in the edge region; removing the first and thesecond exposure regions until a portion of the insulating layer isexposed; removing a portion of the insulating layer exposed by thepositive resistor to form the opening and to expose the edge region ofthe wafer; and removing the remaining positive photoresist.
 5. Themethod of claim 4 , wherein the first and the second exposure steps areperformed in the different steppers.
 6. The method of claim 4 , whereinthe second exposure step is performed without using any mask.
 7. Themethod of claim 4 , wherein the second exposure step is performed byusing a blank mask.
 8. The method of claim 1 , wherein a material of theconductive layer can be polysilicon.